The present invention relates to optimal bus configurations and layouts of components of a multi-processor device in which a plurality of groups of processors are implemented in a single LSI.
In multi-processor devices in which multiple processors of the same architecture and multiple processors of different architectures such as CPU and DSP are implemented over a single semiconductor chip, bus configurations as below have been used. In one configuration, all multiple processors are coupled to a single bus, as described in Non-Patent Document 1 mentioned below. In another configuration, to couple multiple processors using the same protocol to a bus, local buses are provided for each CPU and the local buses are coupled together with a bridge, as described in Non-Patent Document 2 mentioned below.
In the case where all multiple processors are coupled to a single bus, the processors are coupled to the same bus, whether the LSI multi-processor device is equipped with one external bus interface or multiple external bus interfaces.
In the case where multiple local buses are coupled together with a bridge, one processor is coupled to a local bus, the respective local buses are coupled to a single bus master, and a single bus is coupled to an external bus interface.
[Non-Patent Document 1]
Toshiba, EmotionEngine, SCE/IBM/Toshiba, Cell, Feb. 9, 2005, [searched on Jan. 9, 2007] Internet
<http://ascii24.com/news/i/tech/article/2005/02/09/654178-000.html>
[Non-Patent Document 2]
Renesas, G1, February 2006, ISSCC2006 FIG. 29.5.1 “A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor”